? semiconductor components industries, llc, 2006 may, 2006 ? rev. 6 1 publication order number: mac4dcm/d mac4dcm, mac4dcn preferred device triacs silicon bidirectional thyristors designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. features ? small size surface mount dpak package ? passivated die for reliability and uniformity ? blocking voltage to 800 v ? on?state current rating of 4.0 a rms at 108 c ? high immunity to dv/dt ? 500 v/ s at 125 c ? high immunity to di/dt ? 6.0 a/ms at 125 c ? epoxy meets ul 94 v?0 @ 0.125 in ? esd ratings: human body model, 3b 8000 v machine model, c 400 v ? pb?free packages are available maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit peak repetitive off?state voltage (note 1) (t j = ?40 to 125 c, sine wave, 50 to 60 hz, gate open) mac4dcm mac4dcn v drm, v rrm 600 800 v on?state rms current (full cycle sine wave, 60 hz, t c = 108 c) i t(rms) 4.0 a peak non-repetitive surge current (one full cycle sine wave, 60 hz, t j = 125 c) i tsm 40 a circuit fusing consideration (t = 8.3 msec) i 2 t 6.6 a 2 sec peak gate power (pulse width 10 sec, t c = 108 c) p gm 0.5 w average gate power (t = 8.3 msec, t c = 108 c) p g(av) 0.1 w peak gate current (pulse width 10 sec, t c = 108 c) i gm 0.5 a peak gate voltage (pulse width 10 sec, t c = 108 c) v gm 5.0 v operating junction temperature range t j ?40 to 125 c storage temperature range t stg ?40 to 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. v drm and v rrm for all types can be applied on a continuous basis. blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded. triacs 4.0 amperes rms 600 ? 800 volts preferred devices are recommended choices for future use and best overall value. pin assignment 1 2 3 gate main terminal 1 main terminal 2 4 main terminal 2 mt1 g mt2 see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information http://onsemi.com dpak?3 case 369d style 6 dpak case 369c style 6 marking diagrams y = year ww = work week ac4dcx = device code x= m or n g = pb?free package 1 2 3 4 yww ac 4dcxg 1 2 3 4 yww ac 4dcxg
mac4dcm, mac4dcn http://onsemi.com 2 thermal characteristics characteristic symbol max unit thermal resistance, ? junction?to?case ? junction?to?ambient ? junction?to?ambient (note 2) r jc r ja r ja 3.5 88 80 c/w maximum lead temperature for soldering purposes (note 3) t l 260 c electrical characteristics (t j = 25 c unless otherwise noted; electricals apply in both directions) characteristic symbol min typ max unit off characteristics peak repetitive blocking current (v d = rated v drm , v rrm ; gate open) t j = 25 c t j = 125 c i drm, i rrm ? ? ? ? 0.01 2.0 ma on characteristics peak on?state voltage (note 4) (i tm = 6.0 a) v tm ? 1.3 1.6 v gate trigger current (continuous dc) (v d = 12 v, r l = 100 ) mt2(+), g(+) mt2(+), g(?) mt2(?), g(?) i gt 8.0 8.0 8.0 12 18 22 35 35 35 ma gate trigger voltage (continuous dc) (v d = 12 v, r l = 100 ) mt2(+), g(+) mt2(+), g(?) mt2(?), g(?) v gt 0.5 0.5 0.5 0.8 0.8 0.8 1.3 1.3 1.3 v gate non?trigger voltage (continuous dc) (v d = 12 v, r l = 100 ) mt2(+), g(+); mt2(+), g(?); mt2(?), g(?) t j = 125 c v gd 0.2 0.4 ? v holding current (v d = 12 v, gate open, initiating current = 200 ma) i h 6.0 22 35 ma latching current (v d = 12 v, i g = 35 ma) mt2(+), g(+) mt2(+), g(?) mt2(?), g(?) i l ? ? ? 30 50 20 60 80 60 ma dynamic characteristics rate of change of commutating current (v d = 400 v, i tm = 4.0 a, commutating dv/dt = 18 v/ sec, gate open, t j = 125 c, f = 250 hz, cl = 5.0 f, ll = 20 mh, no snubber) (see figure 16) di/dt(c) 6.0 8.4 ? a/ms critical rate of rise of off?state voltage (v d = 0.67 x rated v drm , exponential waveform, gate open, t j = 125 c) dv/dt 500 1700 ? v/ s 2. these ratings are applicable when surface mounted on the minimum pad sizes recommended. 3. 1/8 from case for 10 seconds. 4. pulse test: pulse width 2.0 msec, duty cycle 2%. ordering information device package type package shipping ? mac4dcm?001 dpak?3 369d 75 units / rail mac4dcm?1g dpak?3 (pb?free) 369d 75 units / rail mac4dcmt4 dpak 369c 2500 / tape & reel mac4dcmt4g dpak (pb?free) 369c 2500 / tape & reel mac4dcn?001 dpak?3 369d 75 units / rail mac4dcn?1g dpak?3 (pb?free) 369d 75 units / rail mac4dcnt4 dpak 369c 2500 / tape & reel mac4dcnt4g dpak (pb?free) 369c 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mac4dcm, mac4dcn http://onsemi.com 3 + current + voltage v tm i h symbol parameter v drm peak repetitive forward off?state voltage i drm peak forward blocking current v rrm peak repetitive reverse off?state voltage i rrm peak reverse blocking current voltage current characteristic of triacs (bidirectional device) i drm at v drm on state off state i rrm at v rrm quadrant 1 mainterminal 2 + quadrant 3 mainterminal 2 ? v tm i h v tm maximum on?state voltage i h holding current mt1 (+) i gt gate (+) mt2 ref mt1 (?) i gt gate (+) mt2 ref mt1 (+) i gt gate (?) mt2 ref mt1 (?) i gt gate (?) mt2 ref ? mt2 negative (negative half cycle) mt2 positive (positive half cycle) + quadrant iii quadrant iv quadrant ii quadrant i quadrant definitions for a triac i gt ? + i gt all polarities are referenced to mt1. with in?phase signals (using standard ac lines) quadrants i and iii are used.
mac4dcm, mac4dcn http://onsemi.com 4 figure 1. rms current derating figure 2. on?state power dissipation figure 3. on?state characteristics figure 4. transient thermal response figure 5. typical gate trigger current versus junction temperature figure 6. typical gate trigger voltage versus junction temperature 2.5 4.0 0 i t(rms) , rms on?state current (amps) 125 120 115 i t(rms) , rms on?state current (amps) 3.0 4.0 0 4.0 2.0 1.0 0 5.0 0 v t , instantaneous on?state voltage (volts) 100 10 1.0 0.1 t, time (ms) 1.0 0.1 1.0 0.1 0.01 4.0 ?25 25 ?50 t j , junction temperature ( c) 60 30 20 0 t j , junction temperature ( c) ?25 100 ?50 1.2 0.8 0.6 0.2 25 0 t c , maximum allowable case temperature ( c) p i r (t) , transient resistance (normalized) 110 105 0.5 1.0 1.5 2.0 3.0 3.5 1.0 2.0 3.0 5.0 6.0 1.0 2.0 3.0 10 100 1000 10 k , gate trigger current (ma) i gt 50 125 75 40 0 125 50 75 0.4 v gt , gate trigger voltage(volts) , average power dissipation (watts) (av) , instantaneous on?state current (amps) t 100 50 dc 180 120 90 60 = 30 dc 180 120 90 60 typical @ t j = 25 c maximum @ t j = 25 c maximum @ t j = 125 c z jc(t) = r jc(t) r(t) q3 q2 q1 q3 q2 q1 = conduction angle = conduction angle = 30 10 0 1.0
mac4dcm, mac4dcn http://onsemi.com 5 figure 7. typical holding current versus junction temperature figure 8. typical latching current versus junction temperature figure 9. exponential static dv/dt versus gate?mt1 resistance, mt2(+) figure 10. exponential static dv/dt versus gate?mt1 resistance, mt2(?) figure 11. exponential static dv/dt versus peak voltage, mt2(+) figure 12. exponential static dv/dt versus peak voltage, mt2(?) 75 125 ?50 t j , junction temperature ( c) 60 20 t j , junction temperature ( c) 25 125 ?50 40 20 0 1000 10 k 100 r g?mt1 , gate?mt1 resistance (ohms) 10 k 8.0 k 6.0 k 4.0 k 2.0 k 0 r g?mt1 , gate?mt1 resistance (ohms) 100 15 k 10 k 5.0 k 0 500 600 400 v pk , peak voltage (volts) 10 k 6.0 k 4.0 k 2.0 k 0 v pk , peak voltage (volts) 400 14 k 12 k 6.0 k 2.0 k 0 600 i h , holding current (ma) i static dv/dt (v/ s) static dv/dt (v/ s) 10 0 ?25 0 25 50 100 ?25 0 80 100 120 1000 10 k 700 800 500 800 700 , latching current (ma) l 40 30 50 100 50 75 static dv/dt (v/ s) static dv/dt (v/ s) mt2 positive mt2 negative q2 q3 q1 t j = 125 c v pk = 400 v 600 v 800 v t j = 125 c v pk = 400 v 600 v 800 v gate open t j = 100 c 125 c 110 c gate open t j = 100 c 125 c 110 c 60 8.0 k 10 k 8.0 k 4.0 k
mac4dcm, mac4dcn http://onsemi.com 6 figure 13. typical exponential static dv/dt versus junction temperature, mt2(+) figure 14. typical exponential static dv/dt versus junction temperature, mt2(?) figure 15. critical rate of rise of commutating voltage 125 100 t j , junction temperature ( c) 4.0 k t j , junction temperature ( c) 125 100 10 k 2.0 k 0 5.0 35 0 di/dt(c), rate of change of commutating current (a/ms) 100 10 1.0 commutating voltage (v/ s) 2.0 k 0 105 110 115 120 105 110 12 k 14 k 10 k 8.0 k 115 120 static dv/dt (v/ s) static dv/dt (v/ s) 4.0 k 6.0 k 8.0 k 10 15 gate open v pk = 400 v 800 v 600 v gate open v pk = 400 v 800 v 600 v v pk = 400 v 100 c 75 c t j = 125 c t w v drm (di/dt) c = 6f i tm 1000 f = 1 2 t w dv/dt(c), critical rate of rise of 6.0 k 20 25 30 figure 16. simplified test circuit to measure the critical rate of rise of commutating current (di/dt) c l l 1n4007 200 v + measure i ? charge control charge trigger non-polar c l 51 mt2 mt1 1n914 g trigger control 200 v rms adjust for i tm , 60 hz v ac note: component values are for verification of rated (di/dt) c . see an1048 for additional information.
mac4dcm, mac4dcn http://onsemi.com 7 package dimensions dpak case 369c issue o d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 style 6: pin 1. mt1 2. mt2 3. gate 4. mt2 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
mac4dcm, mac4dcn http://onsemi.com 8 package dimensions dpak?3 case 369d?01 issue b 123 4 v s a k ?t? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? style 6: pin 1. mt1 2. mt2 3. gate 4. mt2 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 mac4dcm/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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